This page is an attempt to be an exhaustive list of Logarithmic Number System references, but naturally it is incomplete. If you have additions or corrections, PLEASE email to the first author of “A Real/Complex Logarithmic Number System ALU” below using the email address (all lower case no space or punctuation): first name middle initial last name at sign this website.

　

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Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of a Low-Power Logarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 11, pp.1421-1433, Nov. 2003.

Khalid H. Abed and R. E. Siferd, ``VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 9, pp.1221-1228, Sept. 2003.

Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of 16-bit Logarithm and Anti-logarithm Converters,” Proceedings of the 43rd IEEE Midwest Circuits and Systems, 2000, vol. 2, pp. 776-779, Aug. 2000.

Nacer Abouchi and Romuald Gallorini, ``Exponential and Logarithmic Functions Using Standard CMOS 0.8 um Technology,” Analog Integrated Circuits and Signal Processing,” vol. 27, no. 1, pp.73-83, Apr. 2001.

Nacer Abouchi, Romuald Gallorini and C. Ruby, ``Exponential and Logarithmic Functions Using Standard CMOS 0.8 um Technology,” Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99), vol. 1, pp. 189-192, Pafos, Cyprus, 5-8 Sept. 1999.

F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``The Gauss-Seidel Fast Affine Projection Algorithm,” Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '02), pp. 109-114, San Diego, 16-18 Oct. 2002.

F. Albu, C. Paleologu and S. Ciochina, ``Analysis of LNS Implementation of the QRD-LSL Algorithms,” Proceedings of the International Symposium on Communications Systems, Networks and Digital Signal Processing (CSNDSP'02), pp. 364-367, Staffordshire, UK, 15-17 July 2002.

F. Albu, J. Kadlec, A. Fagan, A. Hermanek and N. Coleman, ``Analysis of the LNS Implementation of the Fast Affine Projection Algorithms,” Proceedings of ISSC 2002, pp. 251-255, Cork, Ireland, June 2002.

F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``Pipelined Implementations of the A Priori Error-Feedback LSL Algorithm Using Logarithmic Number System,” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 2002, vol. 3, pp. 2681-2684, Orlando, Florida, 13-17 May 2002.

Felix Albu, Jiri Kadlec and J. Nick Coleman Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.

Felix Albu, Jiri Kadlec and J. N. Coleman, ``Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic,” 5th WSES Multiconference on Circuits, Systems, Communications & Computers (CSCC 2001), pp. 517-521, Rethymno, Greece, 2001.

Felix Albu, Jiri Kadlec, R. Matousek, A. Hermanek and J. Nick Coleman, A Comparison of FPGA Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.

M. H. Andoyer, ``Tables Fondamentales pour les Logarithmes d'Addition et de Soustraction,” Bulletin Astronomique, vol. 2, pp. 5-32, 1922.

Mark G. Arnold and Sylvain Collange, ``A Real/Complex Logarithmic Number System ALU,” IEEE Transactions on Computers, preprint, 2010.

http://doi.ieeecomputersociety.org/10.1109/TC.2010.154

M. Arnold, S. Collange, D. Defour, ``Implementing LNS Using Filtering Units of GPUs," Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, pp. 1542-1545, Dallas, Texas, 14 March 2010.

Mark G. Arnold and Sylvain Collange, ``A Dual-Purpose Real/Complex Logarithmic Number System ALU,” IEEE Symposium on Computer Arithmetic, pp. 15-24, Portland, Oregon, 8 June 2009.

Mark G. Arnold and Panos Vouzis, ``A Serial Logarithmic Number System ALU,” EuroMicro Digital System Design DSD, pp. 151-156, Lubeck, Germany, 29 Aug. 2007.

Mark G. Arnold, ``A RISC Processor with Redundant LNS Instructions,” EuroMicro Digital System Design DSD, pp. 475-482, Dubrovnik, Croatia,1 Sept. 2006.

Mark G. Arnold and P. Leong, ``Logarithmic Arithmetic for N-body Simulation,” Proceedings of the Work- in-Progress Session of 31st EuroMicro Conference, Porto, Portugal, pp. 24-25, Porto, P

Mark G. Arnold, ``Approximating Trigonometric Functions with the Laws of Sines and Cosines Using the Logarithmic Number System,” EuroMicro Symposium on Digital Systems Design, pp. 48-53, Porto, Portugal, Aug. 30 - Sept. 3 2005.

Mark G. Arnold and P. Leong, ``Logarithmic Arithmetic for N-body Simulation,” Proceedings of the Work- in-Progress Session of 31st EuroMicro Conference, Porto, Portugal, pp. 24-25, Porto, Portugal, Sept. 3 2005.

M. Arnold and J. Ruan, ``Bipartite Implementation of the Residue Logarithmic Number System,” International Symposium on Optical Science and Technology SPIE Annual Meeting, pp. 196-205. San Diego, Aug. 2005.

Mark G. Arnold, ``The Residue Logarithmic Number System: Theory and Implementation,” 17th International Symposium on Computer Arithmetic, pp. 196-205, Cape Cod, MA, 27-29 June 2005.

Mark G. Arnold, ``LPVIP: A Low-power ROM-Less ALU for Low-Precision LNS,” 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS 3254, pp. 675-684, Santorini, Greece, 15-17 Sept. 2004.

Mark G. Arnold, ``Redundant Logarithmic Arithmetic for MPEG Decoding,” International Symposium on Optical Science SPIE Annual Meeting 2004, Denver, Colorado, 2-6 Aug. 2004.

M. G. Arnold, “Geometric-Mean Interpolation for Logarithmic Number Systems,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), vol. 2, pp. 433-436, Vancouver, Canada, 23-26 May 2004.

M. Arnold, T. Bailey, J. Cowles and C. Walter, ``Fast Fourier Transform Using the Complex Logarithmic Number System,” Journal of VLSI Signal Processing, vol. 33, no. 3, pp.325-335, 2003.

M. G. Arnold, J. Garcia and M. Schulte, ``The Interval Logarithmic Number System,” 16th IEEE International Symposium on Computer Arithmetic(ARITH-16'03), pp. 253-261, Santiago de Compostela, Spain, 15-18 June 2003.

Mark Arnold, ``Asymmetric and Compressed Logarithmic Number Systems for a Multimedia Coprocessor,” Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 1426-1430, Pacific Grove CA, 9-12 Nov. 2003.

Mark Arnold, ``A VLIW Architecture for Logarithmic Arithmetic,” Proceedings of the EuroMicro Digital System Design (DSD'03), pp. 294-302, Antalya, Turkey, 1-6 Sept. 2003.

Mark G. Arnold, ``Iterative Methods for Logarithmic Subtraction,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), pp. 315-325, Hague, Netherlands, 24-26 June 2003.

Mark G. Arnold, ``Avoiding Oddification to Simplify MPEG-1 Decoding with LNS,” IEEE International Workshop on Multimedia Signal Processing, St. Thomas, Virgin Islands, Dec. 2002.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Error Analysis of the Kmetz/Maenner Algorithm,” Journal of VLSI Signal Processing, vol. 33, pp.37-53, Oct. 2002.

Mark G. Arnold, ``LNS for Low-Power MPEG Decoding,” Proceedings of SPIE Advanced Signal Processing, Architectures and Implementations XII, vol. 4791, pp. 369-380, Seattle, Washington, 9-1 July 2002.

Mark G. Arnold, ``Reduced Power Consumption for MPEG Decoding with LNS,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pp. 65-75, San Jose, CA, 17-19 July 2002.

Mark G. Arnold, Logarithmic Number Systems for MPEG and Multimedia Applications, PhD thesis, University of Manchester Institute of Science and Technology, 2002.

Mark G. Arnold, ``An Improved Cotransformation for Logarithmic Subtraction,” Proceedings of the International Symposium on Circuits and Systems (ISCAS'02), pp. 752-755, Scottsdale, Arizona, 26-29 May 2002.

Mark G. Arnold, ``Slide Rules for the 21st Century: Logarithmic Arithmetic as a High-speed, Low-cost, Low-power Alternative to Fixed Point Arithmetic,” Second Online Symposium for Electronics Engineers, 2001.

Mark G. Arnold, Thomas A. Bailey, John R. Cowles and Colin Walter, ``Analysis of Complex LNS FFTs,” Francky Catthoor and Marc Moonen, editors, Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation, pp. 58-69, Antwerp, Belgium, 26-28 Sept. 2001. IEEE Press.

Mark G. Arnold, ``Design of a Faithful LNS Interpolator,” Proceedings of the EuroMicro Digital System Design (DSD'01), pp. 336-345, Warsaw, Poland, 4-6 Sept. 2001.

Mark G. Arnold and Mark D. Winkel, ``A Single-Multiplier Quadratic Interpolator for LNS Arithmetic,” Proceedings of the 2001 International Conference on Computer Design (ICCD'01), pp. 178-183, Austin, Texas, 23-26 Sept. 2001.

M. Arnold and M. Winkel, ``Reconfiguring an FPGA-based RISC for LNS Arithmetic,” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, Proceedings of SPIE, vol. 4525, pp. 88-98, Denver, 21-22 Aug. 2001.

Mark G. Arnold and C. Walter, ``Unrestricted Faithful Rounding is Good Enough for Some LNS Applications,” Proceedings of the 15th International Symposium on Computer Arithmetic, pp. 237-246, Vail, Colorado, 11-13 June 2001.

Mark G. Arnold, ``A Pipelined LNS ALU,” IEEE Workshop on VLSI, Orlando, Florida, 19-20 April 2001.

Mark Arnold, Colin Walter and Freddy Engineer, ``Verilog Transcendental Functions for Numerical Testbenches,” Proceedings of the 10th International HDL Conference, Santa Clara, California, 1 March 2001.

M. G. Arnold, F. N. Engineer and M. D. Winkel, ``AWE: The ARM Workalike Experiment,” WESTCON, San Jose, California, 21 Oct. 1999. www.cs.uwyo.edu/~marnold/awe.html.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems,” IEEE Transactions on Computers, vol. 47, no. 7, pp.777-786, July 1998.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems.,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic(ARITH-13'97), pp. 190-197, Asilomar, California, 6-9 July 1997.

M. G. Arnold, T. A. Bailey, J. J. Cupal and M. D. Winkel, ``On the Cost Effectiveness of Logarithmic Arithmetic for Back-Propagation Training on SIMD Processors,” Proceedings of the 1997 International Conference on Neural Networks, vol. 2, pp. 933-936, Houston, Texas, 9-12 June 1997.

M. G. Arnold, Method and Apparatus for Fast Logarithmic Addition and Subtraction, United States Patent 5,337,266, 9 Aug. 1994.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Applying Features of IEEE 754 to Sign/Logarithm Arithmetic,” IEEE Transactions on Computers, vol. 41, no. 8, pp.1040-1050, Aug. 1992.

M. Arnold, T. Bailey and J. Cowles, ``Comments on `An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System’,” IEEE Transactions on Computers, vol. 41, no. 6, pp.786-788, June 1992.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Initializing RAM-based Logarithmic Processors,” Journal of VLSI Signal Processing, vol. 4, no. 2-3, pp.243-252, May 1992.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Implementing Back-Propagation Neural Nets with Logarithmic Arithmetic,” Proceedings of the International AMSE Conference Neural Networks, vol. 1, pp. 75-86, San Diego, California, May 1991.

M. G. Arnold, T. A. Bailey, J. R. Cowles and J. J. Cupal, ``Redundant Logarithmic Arithmetic,” IEEE Transactions on Computers, vol. 39, no. 8, pp.1077-1086, Aug. 1990.

M. Arnold, T. Bailey, J. Cowles and J. Cupal. ``Redundant Logarithmic Number Systems,” Proceedings of the 9th Symposium on Computer Arithmetic, pp. 144-157, Santa Monica, CA, 6-8 Sept. 1989.

M. G. Arnold, T. A. Bailey and J. R. Cowles, ``Improved Accuracy for Logarithmic Addition in DSP Applications,” Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, vol. 3, pp. 1714-1717, 1988.

Mark G. Arnold, Extending the Precision of the Sign Logarithm Number System, Master's thesis, University of Wyoming, Laramie, 1982.

M. Azarmehr, ``A Multi-Dimensional Logarithmic Number System Based CPU”,

http://www.vlsi.uwindsor.ca/presentations/2006/A Multi-Dimensional Logarithmic Number Dimensional Logarithmic Number_Mahzad.pdf

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P. W. Baker, ``More Efficient Radix-2 Algorithms for Some Elementary Functions,” IEEE Transactions on Computers, 24, pp.1049-1054, Nov. 1975.

G.B. Balaji, K. Balaji, H. Sundararaman, A. Naveen and K. R. Santha, ``Memory Reduction Techniques for Logarithmic Number System," International Conference on Signal Processing, Communications and Networking, Chennai, pp. 410 - 413, 22-24 Feb. 2007.

R. Bannister, D. Gregg, S. Wilson and A. Nisbet, ``FPGA Implementation of an Image Segmentation Algorithm Using Logarithmic Arithmetic," 48th Midwest Symposium on Circuits and Systems, vol. 1, pp. 810 - 813, 7-10 Aug. 2005.

E. H. Bareiss and A. A. Grau, Basics of the CRD Computer, ERDA Report COO-2280-25, Northwestern University, Aug. 1977.

J. L. Barlow, ``On Roundoff Error Distributions in Floating Point and Logarithmetic Arithmetic,” Computing, vol. 34, no. 4, pp.325-347, Oct. 1985.

J. L. Barlow, ``Probabilistic Error Analysis of Gaussian Elimination in Floating Point and Logarithmic Arithmetic,” Computing, vol. 34, no. 4, pp.349-364, Oct. 1985.

J. L. Barlow, Probabilistic Error Analysis of Floating Point and CRD Arithmetics, PhD thesis, Northwestern University, Evanston, Illinois,, 1981.

J. L. Barlow. Probabilistic Error Analysis of Computer Arithmetics, Master's thesis, Northwestern University, Evanston, Illinois, 1979.

Ch. Basetas, I. Kouretas and V. Paliouras, ``Low-Power Digital Filtering Based on the Logarithmic Number System," Lecture Notes in Computer Science Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, pp. 546-555, 2007.

A. Bechtolsheim and T. Gross, ``The Implementation of Addition in Logarithmic Arithmetic,” R. Lyon A. Bell, L. Conway and M. Newell, editors, Proceedings of the MPC79 Multi-University Chip Set Project, Xerox PARC Report, 15 March 1980.

A. Bechtolsheim and T. Gross, ``The Implementation of Addition in Logarithmic Arithmetic,” unpublished paper, Computer Systems Lab, Stanford University, 1980.

N. Belanger, Y. Savaria, ``On the Design of a Double Precision Logarithmic Number System Arithmetic Unit," IEEE North-East Workshop on Circuits and Systems, Gatineau, Que., pp. 241 - 244, 18-21 June 2006.

R. W. Bemer, ``Subroutine Method for Calculating Logarithms,” Communications of the ACM, vol. 1, no. 5, pp.5-7, 1958.

F. Berens, A. Worm, H. Michel and N.When, ``Implementation Aspects of Turbo-Decoders for Future Radio Applications,” Proceedings of the IEEE Vehicular Technology Conference (VTC) Fall 1999, vol. 5, pp. 2601-2605, Amsterdam, Sept. 1999.

L. G. Bleris, P. D. Vouzis, J. G. Garcia, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery,” Control Engineering Practice Journal, Special Issue for ADCHEM Symposium, vol. 15, no. 10, pp 1280-1291, Oct. 2007.

L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Model Predictive Hydrodynamic Regulation of Microflows,” Journal of Micromechanics and Microengineering, vol. 16, pp. 1792-1799, July 2006.

L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``A Co-Processor FPGA Platform for the Implementation of Real-Time Model Predictive Control,” American Control Conference (ACC-06), Minneapolis, Minnesota, 14 June 2006.

L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery Systems and Devices,” International Symposium on Advanced Control of Chemical Processes (ADCHEM-06), Gramado, Brazil, 2 April 2006.

L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Towards Embedded Model Predictive Control for System-on-a-Chip Applications,” Journal of Process Control, vol. 16, no. 3, pp. 255-264, March 2006.

Leonidas Bleris, Mayuresh V. Kothare, Jesus Garcia and Mark G. Arnold, ``Embedded Model Predictive Control for System-On-a-Chip Applications,” Proceedings of the 7th International Symposium on Dynamics and Control of Process Systems, Boston, July 2004.

G. E. Bottomley, R. Ramesh, P. W. Dent and S. Chennakeshu, Despreading of Direct Sequence Spread Spectrum Communications Signals, U.S. Patent 6,005,887, 21 Dec. 1999. Assigned to Ericsson.

E. Boutillon, W. J. Gross and G. Gulak, ``VLSI Architectures for the MAP Algorithm,” IEEE Transactions on Communications, vol. 51, no. 2, pp.175-185, Feb. 2003.

I. F. Numerisches Rechnen. pp. 1018-1020.

T. Brabec, ``Speculatively Redundant Continued Logarithmic Representation,” IEEE Transactions on Computers, vol. 59, no. 11, pp. 1441-1454, Nov. 2010.

R. Brent, ``On the Precision Attainable with Various Floating-Point Number Systems,” IEEE Transactions on Computers, C-vol. 22, no. 6, pp.601-607, June 1973.

T. A. Brubaker and J. C. Becker. ``Multiplication Using Logarithms Implemented with Read-Only Memory,” IEEE Transactions on Computers, vol. 24, no. 8, pp.761-765, Aug. 1975.

T. A. Brubaker, ``Multiplication Using Logarithmic Arithmetic,” Electronic Letters, vol.7, pp.56-58, pp.215-217, 1971.

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O. Callanan, A. Nisbet, E. Ozer, J. Sexton and D. Gregg, ``FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic," 19th IEEE International Parallel and Distributed Processing Symposium, pp. 146b-146b, 04-08 April 2005.

Owen Callanan, David Gregg, Andy Nisbet and Mike Peardon, ``High performance scientific computing using FPGAS with IEEE floating point and logarithmic arithmetic for lattice QCD," International Conference on Field Programmable Logic and Applications, Madrid, pp. 1 - 6, Aug. 2006.

D. Cantor, G. Estrin and R. Turn. ``Logarithm and Exponential Function Evaluation in a Variable Structure Digital Computer,” IRE Transactons on Computers, pp. 155-164, April 1962.

Roger Chamberlain, Eric Hemmeter, Robert Morley and Jason White, ``Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations,” Proceedings of the 36th Annual Simulation Symposium, pp. 249-255, Orlando, Florida, 30 March - 2 April 2003.

http://www.ccrc.wustl.edu/~roger/papers/chmw03.pdf.

Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, John Lockwood Eric Hemmeter, Robert Morley, Ed Richter, Jason White and Huakai Zhang, ``Power Consumption of Customized Numerical Representations for Audio Signal Processing,” 6th High Performance Embedded Computing Workshop, Sept. 2002.

www.ccrc.wustl.edu/~roger/papers/ccdhlmrwz02b.pdf.

Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White and Huakai Zhang, ``Novel Numerical Representations for Low-Power Audio Signal Processing,” International Hearing Aid Research Conference, Aug. 2002.

www.ccrc.wustl.edu/~roger/papers/ccdhlmrwz02.pdf.

D. V. Chandra, ``Error Analysis of FIR Filters Implemented Using Logarithmic Arithmetic,” IEEE Circuits and Systems: Analog and Digital Signal Processing, vol. 45, no. 6, pp.744-747, June 1998.

D. V. Chandra, ``Accumulation of Coefficient Roundoff Error in Fast Fourier Transforms Implemented with Logarithmic Number System,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 35, no. 11, pp.1633-1636, Nov. 1987.

D. V. Chandra, V. P. Nelson and S. A. Stark, ``Distributed Logarithmic FFT Processor,” Proceedings of Southeastcon '81, pp. 210-214, 5-8 April 1981.

C. Chen, ``Error Analysis of LNS Addition/subtraction with Direct-computation Implementation," IET Computers & Digital Techniques, vol. 3, no. 4, pp. 329-337, July 2009.

C. Chen and P. Chow, ``Design of a Versatile and Cost-effective Hybrid Floating-point/LNS Arithmetic Processor," Proceedings of the 17th ACM Great Lakes Symposium on VLSI, Stresa-Lago Maggiore, Italy, pp. 540-545, 11-13 March 2007. Tel: +886-5-24517250 ext. 3738 Email: cychen@fcu.edu.tw

C. Chen, L.W. Liu and J.W. Jou, ``Software Implementation of LNS Arithmetic in an ARM Embedded System," IEEE 13th International Symposium on Consumer Electronics, Kyoto, pp. 1012 - 1014, 25-28 May 2009.

C. Chen and C. H. Yang, ``Pipelined Computation of Very Large Word-Length LNS Addition / Subtraction with Polynomial Hardware Cost,” IEEE Transactions on Computers, vol. 47, no. 9, pp.716-726, July 2000.

C. Chen and C. H. Yang, ``Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables,” Proceedings of the International Conference on Computer Design, pp. 292-297, 5-7 Oct. 1998.

C. C. Chen and Y. Y. Chen, ``Error Analysis of DCT Algorithms in Floating Point and Logarithmic Number Systems,” 9th VLSI Design / CAD Symposium, pp. 313-316, Nan-Tow, Taiwan, 1998.

C. Chen. ``Design and Implementation of a Pipelined and Small Lookup Table LNS Addition / Subtraction Unit with FPGAs,” Aug. 1998.

Chichyang Chen and Rui Lin Chen, ``Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), pp. 337-347, The Hague, The Netherlands, 24-26 June 2003.

Chichyang Chen, Rui-Lin Chen and Ming-Hwa Sheu, ``A Hardware Algorithm for Fast Logarithmic Computation with Exponential Convergence Rate," Journal of the Chinese Institute of Engineers, vol. 28, no. 4, pp. 749-752, July, 2005.

J. M. Chen, T. P. Lin, S. S. Wang, J. Wu and J. C. Liu. ``IIR Filter Design Based on Finite State Machine with LNS Method,” NSCSP, pp. 35-44, Taiwan, Dec. 1987.

Rui-Lin Chen and Chichyang Chen, ``A Hardware Algorithm for Fast Digit On-Line Logarithmic Computation with Exponential Convergence Rate,” Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, Pattaya, Chonburi, pp. 636 - 639, 6-9 May 2009.

T. C. Chen, ``Automatic Computation of Exponentials, Logarithms, Ratios and Square Root,” IBM Journal of Research and Development, pp. 380-388, July 1972.

T. C. Chen, Binary Arithmetic Unit Implementing a Multiplicative Steration for the Exponential, Logarithm, Quotient and Square Root Functions, U.S. Patent, 3,631,230, 28 Dec. 1971. Assigned to IBM.

E. I. Chester and J. N. Coleman, ``Matrix Engine for Signal Processing Applications Using the Logarithmic Number System,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 315-324, San Jose, 17-19 July 2002.

E. I. Chester, ``Online Function Evaluation and Unconventional Computation, or 'State of the Art Computer Arithmetic without the Maths’,” Postgrad Conference, University of Newcastle, Jan. 2000.

E. I. Chester and J. N. Coleman, ``Development of a 32b Real Arithmetic Core for DSP and Graphics,” Proceedings IEEE/IoP PREP99 Conference, Jan. 1999.

E. I. Chester, Design of a 32-bit Logarithmic Arithmetic Logic Unit, Master's thesis, University of Newcastle upon Tyne, Sept. 1996.

K. H. Cho, ``Design of a 40 Digit On-Line Addition Unit in Logarithmic Number System,” Journal of the Chinese Institute of Electrical Engineering, vol. 4, no. 4, pp.275-290, 1997.

C. W. Clenshaw and F. W. J. Olver, ``Beyond Floating Point,” Journal of the ACM, vol. 31, no. 2, pp.319-328, April 1984.

B. Cohn. Tables of Addition and Subtraction Logarithms with Six Decimals. 2nd ed., Scientific Computing Service Ltd., 1939.

J. N. Coleman, Logarithmic Arithmetic System, Patent ID # N21TT2399, Publication # WO9959050, Submitted 29-Aug-02 University of Newcastle. This reference has been placed here because it is probably related to the HSLA project that J. N. Coleman is leading at the University of Newcastle. For more information see http, pp.//webdb2.patent.gov.uk/auril/results.asp?searchtext= N21TT2399&source=browse .

J. N. Coleman, C. I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl and A. Hermanek, ``The European Logarithmic Microprocessor - a QR RLS Application,” Proceedings of the 35th IEEE Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 155-159, Asilomar, 4-7 Nov. 2001.

J. N.Coleman and J. Kadlec, ``Extended Precision Logarithmic Arithmetic,” Proceedings of the 34th IEEE Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 124 - 129, Asilomar, 29 Oct.- 1 Nov. 2000.

J. N. Coleman, E. I. Chester, C. I. Softley and J. Kadlec, ``Correction to `Arithmetic on the European Logarithmic Microprocessor’,” IEEE Transactions on Computers, vol. 49, no. 10, pp.1152, Oct. 2000.

J. N. Coleman, E. I. Chester, C. I. Softley and J. Kadlec, ``Arithmetic on the European Logarithmic Microprocessor,” IEEE Transactions on Computers, vol. 49, no. 7, pp.702-715, July 2000.

J. N. Coleman and E. I. Chester, ``A 32 Bit Logarithmic Number System Processor and its Performance Compared to Floating Point,” 14th IEEE Symposium on Computer Arithmetic, pp. 142-152, Adelaide, Australia, 14-16 April 1999. napier.ncl.ac.uk/HSLA/Docs/arith14paper.pdf.

J. N. Coleman, ``Esprit Project 33544 - HSLA, Open LTR - 2nd phase, A High Speed Logarithmic Arithmetic Unit, Jan. 1999.”

This is a grant proposal that outlines a three year research project that is presently underway at the University of Newcastle to create a commercial grade LNS microprocessor and LNS ASIC cells. For more information, refer to http//www.cordis.lu/esprit/src/23544.htm.

J. N. Coleman, ``Esprit Project 23544 - HSLA, Open LTR - 1st phase, A High Speed Logarithmic Arithmetic Unit, May 1997.”

This is a grant proposal that outlines research conducted at the University of Newcastle upon Tyne. For more information, refer to www.cordis.lu/esprit/src/23544.htm.

J. N. Coleman, ``Errata for `Simplification of the Table Structure in Logarithmic Arithmetic’,” IEE Electronic Letters, no. 22, pp.2103, 1996.

J. N. Coleman, ``Simplification of Table Structure in Logarithmic Arithmetic,” IEE Electronic Letters, vol. 31, no. 22, pp.1905-1906, 26 Oct. 1995.

Sylvain Collange, Florent de Dinechin and Jeremie Detrey, ``Floating Point or LNS: Choosing the Right Arithmetic on an Application Basis,” EuroMicro Digital System Design DSD 2006, pp. 197-203, Dubrovnik, Croatia, Aug. - 1 Sept. 2006.

M. Combet, H. Van Zonneveld and L. Verbeek, ``Computation of the Base Two Logarithm of Binary Numbers,” IEEE Transactions on Electronic Computers, EC-vol. 14, no. 6, pp.863-867, Dec. 1965.

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S. Daniel, S. Ma, K. Warble, S. Pan and S. Wang, Method and Apparatus for Producing Wide Null Antenna Patterns, 9 May 2000. U.S. Patent 6,061,023. Assigned to Motorola.

This patent describes how a special logarithmic DSP processor can be used to do ``beam forming” associated with communication satellites. It is conjectured that this technology was developed for the Iridium satellite system.

D. Das, K. Mukhopadhyaya and B. P. Sinha, ``Implementation of Four Common Functions on an LNS Co-Processor,” IEEE Transactions on Computers, vol. 44, no. 1, pp.155-161, Jan. 1995.

D. DeGryse and B. Guerin, ``A Logarithmic Transcoder,” IEEE Transactions on Computers, C-vol. 21, no. 11, pp. 1165-1168, 1972.

J. Detrey and Florent de Dinechin, ``A VHDL Library of LNS Operations,” 37th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 2227-2231, Pacific Grove, CA, 9-12 Nov. 2003. www.ens-lyon.fr/LIP/Arenaire http, pp.//perso.ens-lyon.fr/jeremie.detrey/FPLibrary/.

J. Detrey and F. de Dinechin, FPlibrary v0. 91 User Documentation,

www. ens-lyon. fr/LIP/Arenaire/Ware/FPLibrary.

K. Dillon, Decibel Addition Circuit, 1981. U.S. Patent 4,290,111, Sep. 15, 1981. Assigned to Singer Co.

Vassil S. Dimitrov and G. A. Jullien, ``Loading the Bases: A New Number Representation with Applications,” IEEE Circuits and Systems Magazine, vol. 3, no. 2, pp.6-23, 2003.

V. Dimitrov, G. Jullien and K. Walus, ``Digital Filtering Using the Multidimensional Logarithmic Number System,” Proceedings of SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XII, vol. 4791, pp. 412-423, Seattle, Dec. 2002.

V. S. Dimitrov, J. Eskritt, L. Imbert, G. A. Jullien and W. C. Miller, ``The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications,” Proceedings of the 15th IEEE Symposium on Computer Arithmetic, pp. 247-254, Vail, CO, June 2001.

V. S. Dimitrov, G. A. Jullien and W. C. Miller, ``Theory and Applications of the Double-Base Number System,” IEEE Transactions on Computers, vol. 48, no. 10, pp.1098-1106, Oct. 1999.

V. S. Dimitrov, G. A. Jullien and W. C. Miller, ``Theory and Applications for a Double-Base Number System,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic (ARITH'97), pp. 44-51, Asilomar, CA, 6-9 March 1997.

Vassil S. Dimitrov, Sadeghi Emamchaie Saeid, Graham A. Jullien and W. C. Miller, ``A Near Canonic Double-Based Number System (DBNS) with Applications in Digital Signal Processing,” Proceedings of the SPIE Conference on Advanced Signal Processing, vol. 2846, pp. 14-16, 2-4 August 1996.

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Florent de Dinechin and Arnaud Tisserand, ``Some Improvements on Multipartite Table Methods,” Proceedings of the 15th Symposium on Computer Arithmetic, pp. 128-135, Vail, Colorado, 2001.

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T. Ebisuzaki, J. Makino, T. Fukushige, M. Taiji, D. Sugimoto, T. Ito and S. K. Okumura ``GRAPE Project: An Overview. PASJ: Publications of the Astronomical Society of Japan, , no. 45, pp.269-278, 1993.

A. D. Edgar and S. C. Lee. ``FOCUS Microcomputer Number System,” Communications of the ACM, vol. 22, no. 3, pp.166-177, March 1979. url, pp.portal.acm.org/ft_gateway.cfm?id=359085&type=pdf.

``Logarithms,'' Encyclopedia Britannica, vol. 31, pp. 290, 1964.

A. M. Engebretson, R. E. Morley, Jr., G. L. Engel and M. P. O'Connell, ``The Development of Devices for the Hearing-Impaired, A Progress Report: Part 1,” Proceedings of the IEEE ASSP Workshop on Applications of Signal Processing to Audio and Acoustics, New Paltz, New York, 15-17 Sep. 1986.

A. M. Engebretson, R. E. Morley, Jr., G. L. Engel and M. P. O'Connell ``The Development of Devices for the Hearing-Impaired, A Progress Report: Part 2,” Proceedings of the IEEE ASSP Workshop on Applications of Signal Processing to Audio and Acoustics, New Paltz, New York, 15-17 Sep. 1986.

G. L. Engel, ``Switched-Capacitor Logarithmic DAC,” Electronics Letters, vol. 35, no. 2, pp.111-112, 21 Jan. 1999.

G. L. Engel, ``Digital Hearing Aids. Report brief,” Southern Illinois University at Edwardsville, 11 Sep. 1998.

url: http, pp.//www.ee.siue.edu/~mentor/research/ANA.html.

G. L. Engel, R. E. Morley, Jr., S. W. Kwa and R. J. Fretz, ``Integrated Circuit Logarithmic Digital Quantizers with Applications to Low-Power Data Interfaces for Speech Processing,” K. Yao H. S. Moscovitz and R. Jain, editors, VLSI Signal Processing, IV. IEEE Press, 1990.

http://www.ee.siue.edu/~mentor/research/ANA.html.

J. A.Erfanian and S. Pasupathy, ``Low-Complexity Parallel Structure Symbol-by-Symbol Detection for ISI Channels,” IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp. 350-353, 1-2 June 1989.

S.J. Eskritt, Inner Product Computational Architectures Using the Double Base Number System, MASc thesis, Univ. of Windsor, 2001.

J. Eskritt, R. Muscedere, G. A. Jullien, V. S. Dimitrov and W. C. Miller, ``A 2-Digit DBNS Filter Architecture,” 2000 IEEE Workshop on Signal Processing Systems (SiPS), pp. 447-456, 11-13 Oct. 2000.

M. H. Etzel, ``Logarithmic Addition for Digital Signal Processing Applications,” IEEE International Symposium on Circuits and Systems, pp. 694-697, 1983.

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D. L. Feucht, ``Logarithmic Addition for Digital Signal Processing Applications,” Journal of Forth Application and Research, vol. 5, no. 2, pp.271-286, 1987. (Note: uses the term ``log-point'' to refer to LNS.).

A. Fletcher, J. C. P. Miller, L. Rosenhead and L. J. Comrie, An Index of Mathematical Tables, vol. 1, pp. 166-168. Addison-Wesley, Massachusetts, 1962.

J. Florence and R. Latham, Log Mixer Circuit, 1988. U.S. Patent 4,734,875, March 29, 1988. Assigned to Singer Co.

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F. Francesconi and F. Maloberti, ``A Low Power Logarithmic A/D Converter,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS β€˜96), vol. 1, pp. 473-476, Atlanta, USA, 12-15 May 1996.

Freedom CPU (a collaborative effort to develop a microprocessor placed in the public domain.)

The draft specification includes some LNS instructions. For more information, refer to the following URL: http//f-cpu.tux.org/manual/part6.html#OptLNS.

M. L. Frey and F. J. Taylor, ``Table Reduction Technique for Logarithmically Architected Digital Filters,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 33, no. 3, pp.718-719, June 1985.

Haohuan Fu, Application-Specific Number Representation, Ph. D. Imperial College London, Department of Computing, Feb. 2009.

H. Fu, O. Mencer and W. Luk, ``FPGA Designs with Optimized Logarithmic Arithmetic, IEEE Transactions on Computers, vol 59, no. 7, pp. 1000-1006, July 2010.

H. Fu, A. Gaffar, O. Mencer, and W. Luk, ``Bit-width Analysis Across Multiple Number Representations,” submitted to IEEE Transactions on Very Large Scale Integration Systems.

H. Fu, O. Mencer and W. Luk, ``Comparing Floating-point and Logarithmic Number Representations for Reconfigurable Acceleration," IEEE International Conference on Field Programmable Technology, Bangkok, pp. 337 - 340, Dec. 2006.

H. Fu, O. Mencer and W. Luk, ``Optimizing Logarithmic Arithmetic on FPGAs," 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 163 - 172, 23-25 April 2007.

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http://www.eecg.toronto.edu/~jayar/research/Transmogrifier1.pdf.

Jesus Garcia, Leonidas Bleris, Mark G. Arnold and Mayuresh V. Kothare, ``LNS Architectures for Embedded Model Predictive Control Processors,” Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), pp. 79-84, Washington DC, 22-25 Sept. 2004.

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http://www.md.kth.se/RTC/ARTIST2/GraduateCourse2008/16_OfflineSchedulingFPGAs_Hanzalek_Sucha.pdf

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Michael Haselman, Michael Beauchamp, Aaron Wood, Scott Hauck, Keith Underwood and K. Scott Hemmert, ``A Comparison of Floating Point and Logarithmic Number Systems for FPGAs,” Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), pp. 181-190, Washington, DC, USA, 2005. IEEE Computer Society.

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Y. Ibrahim, William C. Miller, Graham A. Jullien and Vassil S. Dimitrov. ``DBNS addition using cellular neural networks," International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pp. 3914-3917, 2005.

Interactive Machines Inc., IMI-500 graphics workstation.

This firm built graphics workstations during the 1980's. One model used in 1985, the IMI-500, apparently used LNS to speed up graphics. Note: a full reference will be provided when available.

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K. Johansson, O. Gustafsson and L. Wanhammar, ``Conversion and Addition in Logarithmic Number Systems Using a Sum of Bit-products," 24th Norchip Conference, Linkoping, pp. 39 - 42, Nov. 2006.

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G. A. Jullien, V. S. Dimitrov, B. Li, W. C. Miller, A. Lee and M. Ahmadi, , ``A Hybrid DBNS Processor for DSP Computation,” Proceedings of the 1999 IEEE Intl. Symposium on Circuits and Systems, vol. 1, pp. 5-8, Orlando, USA, 30 May - 2 June 1999.

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L. Jurca, A. Gontean, F. Alexa and D.I. Curiac, ``Single-precision Logarithmic Arithmetic Unit with Floating-point Input/output Data," naun.org

L. A. , ``Jurca. Some Considerations Regarding the Design of a Hybrid Logarithmic, Floating-Point Mathematical Processor,” Symposium of Electronics and Telecommunications, University of Timisoara, Romania, 23-24 Nov. 2000.

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J. Kadlec and F. Albu, , ``Lattice for FPGAs Using Logarithmic Arithmetic,” Electronic Engineering Design, pp. 53-56, 17 July 2002. http, pp.//www.electronicengineering.com/features/fp/OEG20020715S0017.

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J. Kadlec, R. Matousek and M. Licko, , ``FPGA Implementation of Logarithmic Unit Core,” Research report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.

J. Kadlec, A. Hermanek, C. Softley, R. Matousek and M. Licko, , ``32-bit Logarithmic ALU for Handel C 2.1 and Celoxica DK1.” Available: http://www.celoxica.com/.

J. Kadlec, R. Matousek, A. Hermanek and M. Licko, , ``LNS ALU Core for FPGA,” International Conference on Field Programmable Logic and Applications, Villach, Austria, Aug. 27-30 2000. Available: http://www.utia.cas.cz/idealist-east/Vilach/sld001.htm.

J. Kadlec, R. Matousek, C. Vialatte and J. Coleman,, ``Port of Pascal FPGA-logarithmic-unit Simulator to Simulink/RTW,” Proceedings of the 7th Conference MATLAB '99, VSCHT,, pp. 84-90, Praha, 1999. Available: http://www.utia.cas.cz/idealist-east/hslapap/HSLApap.htm.

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M. Kahrs, Digital Audio System Architecture, Kluwer Academic Publishers, March 1998.

Note: among the many topics covered by this book is a description of the 13 bit LNS used in Yamaha music synthesizers during the 1980's.

A. Kawai, T. Fukushige, J. Makino and M. Taiji, ``GRAPE-5: A Special-Purpose Computer for N-Body Simulations. PASJ: Publications of the Astronomical Society of Japan, no. 52, pp.659-676, 2000. Note, pp. this custom VLSI hardware uses a 17-bit LNS to speed up astrophysical calculations. The GRAPE-5 won a Gordon Bell Prize in 1999.

A. Kawai and T. Fukushige, ``$158/Gflops Astrophysical N-Body Simulation with Reconfigurable Add-in Card and Hierarchical Tree Algorithm," Gordon-Bell-Prize Entrant, 2006. http://delivery.acm.org/10.1145/1190000/1188505/a48kawai.pdf?key1=1188505&key2=6955615821&coll=GUIDE&dl=GUIDE&CFID=15151515&CFTOKEN=6184618

Faisal M. Khan, Mark Arnold and William M. Pottenger, ``Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems.” Proceedings of the Euromicro Symposium on Digital System Design (DSD'04), pp. 254-261, Rennes, France, 31 Aug. - 3 Sept. 2004.

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T. Kurokawa and T. Mizukoshi, ``Computer Graphics Using Logarithmic Number Systems,” IEICE Transactions, vol. 74, no. 2, pp.447-451, 1991.

T. Kurokawa and T. Mizukoshi, ``A Fast and Simple Method for Curve Drawing--A New Approach Using Logarithmic Number Systems,” Journal of Information Processing, vol. 14, no. 2, pp.144-152, 1991.

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T. Kurokawa and T. Mizukoshi, ``Fast Method of Geometrical Picture Transformation Using Logarithmic Number Systems and Its Application for Computer Graphics,” Proceedings of SPIE, Visual Communications and Image Processing '90, vol. 1360, pp. 1479-1490, Lausanne, Switzerland, October 1-4 1990.

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F. Lai, ``The Efficient Implementation and Analysis of a Hybrid Number System Processor,” IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 40, no. 6, pp.382-392, June 1993.

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Barry Lee and Neil Burgess, ``A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA,” 13th International Conference on Field Programmable Logic and Applications, Springer-Verlag, vol. 2778, pp. 808-817, Lisbon Portugal, 1-3 Sept 2003.

Barry Lee and Neil Burgess, ``Some Results on Taylor-Series Function Approximation on FPGA,” 37th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, 9-12 Sept. 2003.

B. E. Lee and Neil Burgess, ``A Parallel Look-up Logarithmic Number System Addition/Subtraction Scheme for FPGA,” IEEE International Conference on Field-Programmable Technology (FPT'03), University of Tokyo, 15-17 Dec. 2003.

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Note: the GRAPE systems are special-purpose computers designed for astrophysical calculations. The GRAPE-1, GRAPE-3 and GRAPE-5 models are based on LNS. The GRAPE-5 model won a Gordon Bell Prize in 1999.

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This paper describes analog circuits that process logarithmically encoded signals and references some digital LNS papers.

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V. Paliouras, J. Dagres, P. Tsakalides and T. Stouraitis, VLSI Architectures for Blind Equalization Based on Fractional-Order Statistics,” The 8th IEEE International Conference on Electronics, Circuits and Systems, vol. 2, pp. 799-802, Malta, 2-5 Sept. 2001.

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V. Paliouras and T. Stouraitis, ``Signal Activity and Power Consumption Reduction Using the Logarithmic Number System,” The 2001 IEEE International Symposium on Circuits and Systems, vol. 2, pp. 653-656, Sydney, Australia, 6-9 May 2001.

V. Paliouras and T. Stouraitis, ``Logarithmic Number System for Low-Power Arithmetic,” Proceedings of the PATMOS 2000, International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 285-294, Gottingen, Germany, 13-15 Sep. 2000.

V. Paliouras, J. Karagiannis, G. Aggouras and T. Stouraitis, ``A Very-Long Instruction Word Digital Signal Processor Based on Logarithmic Number System,” Proceedings of the International Conference on Electronics, Circuits and Systems, vol. 59-62, pp. 59-63, 7-10 Sept. 1998.

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This paper describes logarithmic addition using the residue number system.

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One of the optimizations mentioned in this paper involves logarithmic addition.

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J. Ruan and Mark G. Arnold, ``New Cost Function for Motion Estimation in MPEG Encoding Using LNS,” International Symposium on Optical Science SPIE Annual Meeting 2004, Denver, Colorado, 2-6 August 2004.

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Jan Schier and Jiri Kadlec, ``Using Logarithmic Arithmetic for FPGA Implementation of the Givens Rotations,” Sixth Baiona Workshop on Signal Processing in Communications, 8-10 Sept. 2003. http://www.baionaworkshop.org/program.html.

V. P. Shenoy and F.J. Taylor, ``Error Analysis of LMS Adaptive Digital Filter Implemented with Logarithmic Number System,” Proceedings of the 1984 IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 30.10.1-30.10.4, March 19-21, 1984.

V. P. Shenoy and F. J. Taylor, ``On Short Term Autocorrelator Implemented with Logarithmic Number System,” Proceedings of the Symposium on Circuits and Systems, p. 401, Aug. 1982.

G. L. Sicuranza, ``On Efficient Implementations of 2-D Digital Filters Using Logarithmic Number Systems,” IEEE Transactions on Acoustics, Speech and Signal Processing, ASSP-31, pp. 877-885, Aug. 1983.

G. L. Sicuranza, ``Fast Realisation of 2-D Digital Filters Using Logarithmic Number Systems,” Electronics Letters, vol. 19, no. 12, pp.449-450, June 9 1983.

G. L. Sicuranza, ``On the Accuracy of 2-D Digital Filter Realizations Using Logarithmic Number System,” Proceedings of the ICASSP'82, pp. 48-51, 1982.

G. L. Sicuranza, ``2-D Digital Filters Using Logarithmic Number Systems,” Electronics Letters, vol. 17, no. 22, pp. 854-855, Oct. 29 1982.

K. Simons, ``N-Logs: A New Number Language for Scientific Computers,” Dr. Dobb’s Journal, vol. 5, no. 10, pp. 4-9, Dec. 1980.

J. Skog, O. Vainio and J. Nurmi, ``Processor Architecture for Logarithmic Signal Processing,” Proceedings of the TUT Symposium on Signal Processing '94, Tampere, Finland, May 20 1994.

J. O. Smith, ``Logarithmic Number Systems for Digital Audio,” Center for Computer Research in Music and Acoustics (CCRMA), Stanford University.

http://www-ccrma.stanford.edu/~jos/log/Logarithmic_Number_Systems.html

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Physics E: Sci. Instrum, 15, pp. 1114-1118, 1982.

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.

~ S ~

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A. Stolzle, S. Narayanaswamy, H. Murveit, J. M. Rabaey and R. W. Brodersen, ``Integrated Circuits for a Real-Time Large-Vocabulary Continuous Speech Recognition System,” IEEE Journal of Solid-State Circuits, vol. 26, no. 1, pp. 2-11, Jan. 1991.

T. Stouraitis and V. Paliouras, ``Considering the Alternatives in Low-Power Design,” IEEE Circuits and Devices Magazine, vol. 1, no. 4, pp.22-29, July 2001.

T. Stouraitis and C. Chen, ``Hybrid Signed Digit Logarithmic Number System Processor,” IEEE Proceedings of Computers and Digital Techniques, vol. 140, pp. 205-210, 1993.

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T. Stouraitis, ``Hybrid Floating-Point/Logarithmic Number System Digital Signal Processor,” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 1079-1082, May 23-26 1989.

T. Stouraitis, ``Efficient VLSI Implementation of Logarithmic Signal Processors,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1540-1543, Portland, Oregon, May 9-11 1989.

T. Stouraitis and F. J. Taylor, ``Floating-Point to Logarithmic Encoder Error Analysis,” IEEE Transactions on Computers, vol. 37, no. 7, pp. 858-863, July 1988.

T. Stouraitis and F. J. Taylor, ``Analysis of Logarithmic Number Systems Processors,” IEEE Transactions on Circuits and Systems, vol. 35, no. 5, pp. 519-527, May 1988.

T. Stouraitis, Logarithmic Number System Theory, Analysis and Design, PhD thesis, Univ. of Florida, Gainesville, Florida, 1986.

T. Stouraitis, G. M. Papadourakis and A. Skavantzos, ``An Adaptive Radix Reconfigurable Logarithmic Processor for Signal Processing,” Proceedings of the IASTED International Symposium, pp. 333-336, Paris, France, June 19-21 1985.

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P. Sucha, Z. Hanzalek, A. Hermanek and J. Schier, ``Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design: Implementation of Finite Interval Constant Modulus Algorithm," The Journal of VLSI Signal Processing, vol. 46, No. 1, pp. 35-53, January 2007.

P. Sucha, Z. Hanzalek, A. Hermanek and J. Schier, ``Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm," Proceedings of the International Symposium on Industrial Embedded Systems (IES '06), Antibes Juan-les-Pins, France, pp. 1-10, Oct. 2006.

P. Sucha and Z Hanzalek, ``Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation," http://dce.felk.cvut.cz/hanzalek/publications/Hanzalek08e.pdf

P. Sucha, Z. Pohl and Z. Hanzalek, ``Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit," 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), Toronto, pp. 404 - 412, 25-28 May 2004.

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More recent publications are at:

http://www.ee.siue.edu/~mentor/research/VLSI.html, http://www.ee.siue.edu/~mentor/research/ANA.html,

http: //www.ee.siue.edu/~mentor/research/DHA.html.

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E. E. Swartzlander, D. Chandra, T. Nagle and S. A. Starks, ``Sign/Logarithm Arithmetic for FFT Implementation,” IEEE Transactions on Computers, C-32, pp.526-534, 1983.

Earl E. Swartzlander and Barry K. Gilbert, ``Arithmetic for Ultra-High-Speed Tomography,” IEEE Transactions on Computers, vol. 29, no. 5, pp.341-353, 1980.

E. Swartzlander, ``Comment on 'The Focus Number System',” IEEE Transactions on Computers, vol. 28, no. 9, pp.693, Sept. 1979.

E. Swartzlander and B. K. Gilbert, ``High Speed Computerized Tomography,” Proceedings of the Society of Photo-Optical Instrumentation Engineers, vol. 119, pp. 299-306, 1977.

E. E. Swartzlander and A. G. Alexopoulos, ``The Sign/Logarithm Number System,” IEEE Transactions on Computers, vol. 24, no. 12, pp.1238-1242, Dec. 1975.

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F. J. Taylor, R. Gill, J. Joseph and J. Radke, ``A 20 Bit Logarithmic Number System Processor,” IEEE Transactions on Computers, 37, pp.190-199, 1988.

F. J. Taylor, Hybrid Floating Point/Logarithmic Number Arithmetic Processor, United States Patent 4,720,809, Jan. 19 1988. Assigned to Univ. of Florida.

F. J. Taylor, ``Reconfigurable Binary/RNS/LNS Architecture for DSP,” Proceedings of the 1987 International Conference on Acoustics, Speech and Signal Processing, pp. 503-506, April 6-9 1987.

F. J. Taylor, ``Hybrid Floating-Point Logarithmic Number System Processor,” IEEE Transactions on Circuits and Systems, vol. 32, no. 1, pp. 92-95, Jan. 1985.

F. J. Taylor, ``A Logarithmic Arithmetic Unit for Signal Processing,” Proceedings ICASSP, pp. 44.10.1-44.10.4, 1984.

F. J. Taylor, ``An Extended Precision Logarithmic Number System,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 31, no. 1, pp.232-234, Feb. 1983.

D.H.Y. Teng, Hu Song and Dinh Anh, ``A Technology-Independent Logarithmic Converter IP Block," Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, pp. 1376-1379, 22-26 April 2007

Russell Tessier and Wayne Burleson, ``Reconfigurable Computing for Digital Signal Processing: A Survey,” Journal of VLSI Signal Processing, vol. 28, no. 1-2, pp. 7-27, 2001.

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http://www.cse.cuhk.edu.hk/~phwl/publications.html.

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P. R. Turner, ``Complex SLI Arithmetic, pp. Representation, Algorithms and Analysis,” Proceedings of the 11th Symposium on Computer Arithmetic, pp. 18-25, Windsor, Ontario, Canada, June 29-July 4 1993.

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http://www.usna.edu/AcResearch/sumres97/MATHDEPT.htm

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Y. Uchiyama and H. Suzuki, ``Electronic Musical Instrument Forming Tones by Wave Computation,” United States Patent 4,616,546, Oct. 14 1986. Assigned to Yamaha.

This patent uses logarithmic arithmetic to implement FM synthesis for Yamaha's musical synthesizers. For more information refer to Applications of Digital Signal Processing to Audio and Acoustics (M. Kahrs and K. Branderburg editors, Kluwer Academic Publishers, Norwell, MA, 1998) or see

http://www.musemagic.com/papers/DSPworld.html.

PRO-DASP VIVA 2002, 2002. Project at the Univ. of Hamburg is developing a power efficient macro-module library for audio signal processing. Some of the designs apparently use LNS. For more information see

http://ima-www.informatik.uni-hamburg.de/Papers/2002/prodasp_viva_02.html.

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O. Vainio, ``Biased Logarithmic Arithmetic in FIR Filters," Electronics Letters, vol. 41, no.10, 580-581, 12 May 2005.

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Richard Van Nee and Ramjee Prasad, OFDM Wireless Multimedia Communications, Artech House Publishers, 2000.

R. vanDrunen, M. Diepenhorst, G. Poppinga and L. Spaanenburg, ``32-bit Complex-Arithmetic Integer Logic Unit with Dynamic Accuracy,” Proceedings of the Custom Integrated Circuits Conference, pp. 33-36, Santa Clara, 1995.

R. vanDrunen, L. Spaanenburg, P. Lucassen, J.A.G. Nijhuis and J.T. Udding, ``Arithmetic for Relative Accuracy. Proceedings of the 12th Symposium on Computer Arithmetic, pp. 208-209, Bath, England, July 19-21 1995.

N. Venkateswaran, Vasanth Ramesan, R. Subramanian and S. Praveen, ``A Mixed Number System Based Low Power High Performance Arithmetic Processor for DSP Applications,” Proceedings of the International Signal Processing Conference (ISPC'03), vol. 2, pp. 421-424, Dallas, Texas, 1-3 April 2003.

V. L. Volkov and P. V. Pakshin, ``Logarithmic Number System in Control Algorithms and Information Processing,” Soviet Journal of Computer and Systems Sciences, vol. 30, no. 1, pp.132-138, Jan.-Feb. 1992.

P. D. Vouzis, S. Collange and M. G. Arnold, ``A Novel Cotransformation for LNS Subtraction,” Journal of VLSI Signal Processing, vol. 59, no. 1, pp. 29-40, Jan. 2010.

P. D. Vouzis, L. G. Bleris, M. G. Arnold and M. V. Kothare, ``A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control,” IEEE Transactions on Control Systems Technology, vol. 17, no. 5, pp. 1006-1017, Sept. 2009.

P. D. Vouzis, S. Collange and M. G. Arnold, ``Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction,” Euromicro Conference on Digital System Design, pp. 85-93, Lubeck, Germany, 29 Aug. 2007.

P. D. Vouzis, S. Collange, M. G. Arnold and M. Kothare, ``Monte-Carlo Logarithmic Number System for Model Predictive Control,” Proceedings of the 17th International Conference on Field Programmable Logic and Applications, pp. 453-458, Amsterdam, Netherlands, 27 Aug. 2007.

P. D. Vouzis, S. Collange and M. G. Arnold, ``LNS Subtraction Using Novel Cotransformation and/or Interpolation,” Application Specific Systems, Architectures and Processors, pp. 107-114, Montreal, Quebec, 9 July 2007.

P. D. Vouzis, M. G. Arnold, L. G. Bleris, M. V. Kothare and Yongho Cha, ``A Coprocessor Accelerator for Model Predictive Control,” Proceedings of the Fifth Workshop on Optimization for DSP and Embedded Systems, pp. 76-77, San Jose, CA, 11 March 2007.

P. D. Vouzis, M. G. Arnold, L. G. Bleris and M. V. Kothare, ``Model Predictive Control for Embedded Applications,” AIChE Annual Meeting, Nov. 2006.

P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``Evaluating Robustness of Model Predictive Control Using Monte-Carlo Simulations,” AIChE Annual Meeting, Nov. 2006.

P. D. Vouzis, L. G. Bleris, M. G. Arnold and M. V. Kothare, ``A Custom-Made Algorithm-Specific Processor for Model Predictive Control,” International Symposium of Industrial Electronics (ISIE06), Montreal, Quebec, pp. 228-233, 9 July 2006.

Panagiotis Vouzis and Mark Arnold, ``A Parallel Search Algorithm for CLNS Addition Optimization,” IEEE International Symposium on Circuits and Systems, pp. 2417-2420, Kos, Greece, 21-24 May 2006.

P. Vouzis, L. G. Bleris, M. V. Kothare and M. G. Arnold, ``Towards a Co-design Implementation of a System for Model Predictive Control,” AIChE Annual Meeting, Cincinnati, Ohio, Nov. 2005.

P. Vouzis, M. G. Arnold and V. Paliouras, ``Using CLNS for FFTs in OFDM Demodulation of UWB Receivers,” The IEEE International Symposium on Circuits and Systems 2005, vol. 4, pp. 3954-3957, Kobe, Japan, 23-26 May 2005.

Panayiotis Vouzis and Vassilios Paliouras, ``Optimal Logarithmic Representation in Terms of SNR Behavior,” 14th International Workshop on Power and Timing Modeling, Optimization and Simulation LNCS 3254, number 3254, pp. 760-769, Santorini, Greece, 15-17 Sept. 2004.

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Y. Wan and C. L. Wey, ``Efficient Algorithms for Binary Logarithmic Conversion and Addition,” IEEE Proceedings, Computers and Digital Techniques, vol. 146, pp. 168-176, May 1999.

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This summary of Dr. An Wang's career gives an overview of the LOCI (LOgarithmic Computing Instrument) desktop calculator that Wang Labs introduced in 1964.

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Yan Wang, Hing Mo Lam, Chi Ying Tsui, R. S. Cheng and Wai Ho Mow, ``Low Complexity OFDM Receiver Using Log-FFT for Coded OFDM System,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'02), vol. 3, pp. 445-448, Scottsdale, Arizona, 26-29 May 2002.

Yan Wang, C.Y. Tsui, R.S. Cheng and Wai Ho Mow, ``Performance Study of OFDM Receiver Using FFT Based on Log Number System,” IEEE Semiannual Vehicular Technology Conference (VTC-02), vol. 55, pp. 1257-1259, Birmingham, Alabama, USA, 6-9 May 2002.

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T. A. Williams, Logarithmic Arithmetic Logic Unit, United States Patent 4,682,302, July 21 1987. Assigned to Motorola.

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S. Young, G. Evermann, D. Kershaw, G. Moore, J. Odell, D. Ollason, V. Valtchev and P. Woodland, The HTK Book (for HTK Version 3.1), Cambridge University Engineering Department, Dec. 2001. Available: http, //htk.eng.cam.ac.uk/.

Note: HTK is a popular toolkit (based on a 15-bit LNS) that is widely used by researchers to implement Hidden Markov Models for speech recognition.

M. I. Youssef, ``A New Stable Second-Order Section for Recursive Digital Filters Realized with Logarithmic Arithmetic,” 11th Mediterranean Electrotechnical Conference, MELCON 2002, pp. 308-314, May 7-9 2002.

E. C. Yowell and G. Blanch, ``A Guide to Tables on Punched Cards,” MTAC, v. 5, pp.185-202, 1951.

L. K. Yu and D. M. Lewis, ``A 30-bit Integrated Logarithmic Number System Processor,” IEEE Journal of Solid-State Circuits, vol. 26, no. 10, pp.1433-1440, Oct. 1991.

L. Yu, Design and Implementation of a 30-bit Logarithmic Number Processor, Master's thesis, Univ. of Toronto, Jan. 1990.

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P. Zdenek, T. Milan and K. Jiri, ``Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA,” EURASIP Journal on Advances in Signal Processing, vol. 2008, Article ID 394201, 11 pages, 2008. doi:10.1155/2008/394201

G. Zelniker and F. J. Taylor, ``A Reduced Complexity Finite Field ALU,” IEEE Transactions on Circuits and Systems, vol. 38, no. 12, pp.1571-1573, Dec. 1991.

Wenjing Zhang, G. A. Jullien and V. S. Dimitrov, ``A Programmable Base 2D-LNS MAC with Self-generated Lookup Tables,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), vol. 2, pp. 789-792, Vancouver, Canada, 23-26 May 2004.