MyLibrary

[1]	Khalid H. Abed and R. E. Siferd. CMOS VLSI Implementation of a Low-Power Logarithmic Converter. IEEE Transactions on Computers, 52(11):1421-1433, Nov. 2003. [ bib ]
[2]	Khalid H. Abed and R. E. Siferd. VLSI Implementation of a Low-Power Antilogarithmic Converter. IEEE Transactions on Computers, 52(9):1221-1228, Sept. 2003. [ bib ]
[3]	Khalid H. Abed and R. E. Siferd. CMOS VLSI Implementation of 16-bit Logarithm and Anti-logarithm Converters. In Proceedings of the 43^rd IEEE Midwest Circuits and Systems, 2000, volume 2, pages 776-779, Aug. 2000. [ bib ]
[4]	Nacer Abouchi and Romuald Gallorini. Exponential and Logarithmic Functions Using Standard CMOS 0.8 um Technology. Analog Integrated Circuits and Signal Processing, 27(1):73-83, Apr. 2001. [ bib ]
[5]	Nacer Abouchi, Romuald Gallorini, and C. Ruby. Exponential and logarithmic functions using standard CMOS 0.8 um technology. In Proceedings of the 6^th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99), volume 1, pages 189-192, Pafos, Cyprus, 5-8 Sept. 1999. [ bib ]
[6]	F. Albu, Jiri Kadlec, Nick Coleman, and Anthony Fagan. The Gauss-Seidel Fast Affine Projection Algorithm. In Proceedings of the IEEE IEEE Workshop on Signal Processing Systems (SIPS '02), pages 109-114, San Diego, 16-18 Oct. 2002. [ bib ]
[7]	F. Albu, C. Paleologu, and S. Ciochina. Analysis of LNS Implementation of the QRD-LSL Algorithms. In Proceedings of International Symposium on Communications Systems, Networks and Digital Signal Processing (CSNDSP'02), pages 364-367, Staffordshire, UK, 15-17 July 2002. [ bib ]
[8]	F. Albu, J. Kadlec, A. Fagan, A. Hermanek, and N. Coleman. Analysis of the LNS Implementation of the Fast Affine Projection Algorithms. In Proceedings of ISSC 2002, pages 251-255, Cork, Ireland, June 2002. [ bib ]
[9]	F. Albu, Jiri Kadlec, Nick Coleman, and Anthony Fagan. Pipelined Implementations of the A Priori Error-Feedback LSL Algorithm Using Logarithmic Number System. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002, volume 3, pages 2681-2684, Orlando, Florida, 13-17 May 2002. [ bib ]
[10]	Felix Albu, Jiri Kadlec, and J. Nick Coleman. Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic. Research report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001. [ bib ]
[11]	Felix Albu, Jiri Kadlec, and J. N. Coleman. Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic. In 5^th WSES Multiconference on Circuits, Systems, Communications & Computers (CSCC 2001), pages 517-521, Rethymno, Greece, 2001. [ bib ]
[12]	Felix Albu, Jiri Kadlec, R. Matousek, A. Hermanek, and J. Nick Coleman. A Comparison of FPGA Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic. Research report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001. [ bib ]
[13]	M. H. Andoyer. Tables fondamentales pour les logarithmes d'addition et de soustraction. In Bulletin Astronomique, volume 2, pages 5-32, 1922. [ bib ]
[14]	Mark G. Arnold. A RISC Processor with Redundant LNS Instructions. In EuroMicro Digital System Design DSD, pages 475-482, Dubrovnik, Croatia, Aug.-1 Sept. 2006. [ bib ]
[15]	Mark G. Arnold. Approximating Trigonmetric Functions with the Laws of Sines and Cosines Using the Logarithmic Number System. In EuroMicro Symposium on Digital Systems Design, pages 48-53, Porto, Portugal, Aug. 30 - Sept. 3 2005. [ bib ]
[16]	Mark G. Arnold and P. Leong. Logarithmic Arithmetic for N-body Simulation. In Proceedings of the Work- in-Progress Session of 31th EuroMicro Conference, Porto, Porgugal, pages 24-25, Porto, Portugal, Sept. 3 2005. [ bib ]
[17]	Mark G. Arnold. The Residue Logarithmic Number System: Theory and Implementation. In 17^th International Symposium on Computer Arithmetic, pages 196-205, Cape Code, MA, 27-29 June 2005. [ bib ]
[18]	Mark G. Arnold. LPVIP: A Low-power ROM-Less ALU for Low-Precision LNS. In 14^th International Workshop on Power and Timing Modeling, Optimization and Simulation LNCS 3254, pages 675-684, Santorini, Greece, 15-17 Sept. 2004. [ bib ]
[19]	Mark G. Arnold. Redundant logarithmic arithmetic for MPEG decoding. In International Symposium on Optical Science SPIE Annual Meeting 2004, Denver, Colorado, 2-6 Aug. 2004. [ bib ]
[20]	M. G. Arnold. Geometric-Mean Interpolation for Logarithmic Number Systems. In Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), volume 2, pages 433-436, Vancouver, Canada, 23-26 May 2004. [ bib ]
[21]	M. Arnold, T. Bailey, J. Cowles, and C. Walter. Fast Fourier Transform Using the Complex Logarithmic Number System. Journal of VLSI Signal Processing, 33(3):325-335, 2003. [ bib ]
[22]	M. G. Arnold, J. Garcia, and M. Schulte. The Interval Logarithmic Number System. In 16^th IEEE International Symposium on Computer Arithmetic(ARITH-16'03), pages 253-261, Santiago de Compostela, Spain, 15-18 June 2003. [ bib ]
[23]	Mark Arnold. Asymmetric and Compressed Logarithmic Number Systems for a Multimedia Coprocessor. In Proceedins of the 37^th Asilomar Conference on Signals, Systems, and Computers, pages 1426-1430, Pacific Grove CA, 9-12 Nov. 2003. [ bib ]
[24]	Mark Arnold. A VLIW Architecture for Logarithmic Arithmetic. In Proceedings of the EuroMicro Digital System Design (DSD'03), pages 294-302, Antalya, Turkey, 1-6 Sept. 2003. [ bib ]
[25]	Mark G. Arnold. Iterative Methods for Logarithmic Subtraction. In The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), pages 315-325, Hague, Netherlands, 24-26 June 2003. [ bib ]
[26]	Mark G. Arnold. Avoiding Oddification to Simplify MPEG-1 Decoding with LNS. In IEEE International Workshop on Multimedia Signal Processing, St. Thomas, Virgin Islands, Dec. 2002. [ bib ]
[27]	M. Arnold, T. Bailey, J. Cowles, and J. Cupal. Error Analysis of the Kmetz/Maenner Algorithm. Journal of VLSI Signal Processing, 33:37-53, Oct. 2002. [ bib ]
[28]	Mark G. Arnold. LNS for Low-Power MPEG Decoding. In Proceedings of SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations XII, volume 4791, pages 369-380, Seattle, Washington, 9-1 July 2002. [ bib ]
[29]	Mark G. Arnold. Reduced Power Consumption for MPEG Decoding with LNS. In The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pages 65-75, San Jose, CA, 17-19 July 2002. [ bib ]
[30]	Mark G. Arnold. Logarithmic Number Systems for MPEG and Multimedia Applications. PhD thesis, University of Manchester Institute of Science and Technology, 2002. [ bib ]
[31]	Mark G. Arnold. An Improved Cotransformation for Logarithmic Subtraction. In Proceedings of the International Symposium on Circuits and Systems (ISCAS'02), pages 752-755, Scottsdale, Arizona, 26-29 May 2002. [ bib ]
[32]	Mark G. Arnold. Slide Rules for the 21^st Century: Logarithmic Arithmetic as a High-speed, Low-cost, Low-power Alternative to Fixed Point Arithmetic. In Second Online Symposium for Electronics Engineers, 2001. [ bib ]
[33]	Mark G. Arnold, Thomas A. Bailey, John R. Cowles, and Colin Walter. Analysis of Complex LNS FFTs. In Francky Catthoor and Marc Moonen, editors, Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation, pages 58-69, Antwerp, Belgium, 26-28 Sept. 2001. IEEE Press. [ bib ]
[34]	Mark G. Arnold. Design of a Faithful LNS Interpolator. In Proceedings of the EuroMicro Digital System Design (DSD'01), pages 336-345, Warsaw, Poland, 4-6 Sept. 2001. [ bib ]
[35]	Mark G. Arnold and Mark D. Winkel. A Single-Multiplier Quadratic Interpolator for LNS Arithmetic. In Proceedings of the 2001 International Conference on Computer Design (ICCD'01), pages 178-183, Austin, Texas, 23-26 Sept. 2001. [ bib ]
[36]	M. Arnold and M. Winkel. Reconfiguring an FPGA-based RISC for LNS Arithmetic. In Reconfigureable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III,Proceedings of SPIE, volume 4525, pages 88-98, Denver, 21-22 Aug. 2001. [ bib ]
[37]	Mark G. Anold and C. Walter. Unrestricted Faithful Rounding is Good Enough for Some LNS Applications. In Proceedings of the 15^th International Symposium on Computer Arithmetic, pages 237-246, Vail, Colorado, 11-13 June 2001. [ bib ]
[38]	Mark G. Arnold. A Pipelined LNS ALU. In IEEE Workshop on VLSI, Orlando, Florida, 19-20 April 2001. [ bib ]
[39]	Mark Arnold, Colin Walter, and Freddy Engineer. Verilog Transcendental Functions for Numerical Testbenches. In Proceedings of the 10^th International HDL Conference, Santa Clara, California, 1 March 2001. [ bib ]
[40]	M. G. Arnold, F. N. Engineer, and M. D. Winkel. AWE: The ARM Workalike Experiment. In WESTCON, San Jose, California, 21 Oct. 1999. `www.cs.uwyo.edu/~marnold/awe.html`. [ bib ]
[41]	M. G. Arnold, T. A. Bailey, J. R. Cowles, and M. D. Winkel. Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems. IEEE Transactions on Computers, 47(7):777-786, July 1998. [ bib ]
[42]	M. G. Arnold, T. A. Bailey, J. R. Cowles, and M. D. Winkel. Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems. In Proceedings of the 13^th IEEE Symposium on Computer Arithmetic(ARITH-13'97), pages 190-197, Asilomar, California, 6-9 July 1997. [ bib ]
[43]	M. G. Arnold, T. A. Bailey, J. J. Cupal, and M. D. Winkel. On the Cost Effectiveness of Logarithmic Arithmetic for Back-Propagation Training on SIMD Processors. In Proceedings of the 1997 International Conference on Neural Networks, volume 2, pages 933-936, Houston, Texas, 9-12 June 1997. [ bib ]
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[94]	J. N. Coleman, C. I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl, and A. Hermanek. The European Logarithmic Microprocessor - a QR RLS Application. In Proceedings 35^th IEEE Asilomar Conference on Signals, Systems and Computer, volume 1, pages 155-159, Asilomar, 4-7 Nov. 2001. [ bib ]
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[99]	J. N. Coleman. Esprit Project 33544 - HSLA, Open LTR - 2^nd phase, A High Speed Logarithmic Arithmetic Unit, Jan. 1999. This is a grant proposal that outlines a three year research project that is presently underway at the University of Newcastle to create a commercial grade LNS microprocessor and LNS ASIC cells. For more information, refer to http://www.cordis.lu/esprit/src/23544.htm. [ bib ]
[100]	J. N. Coleman. Esprit Project 23544 - HSLA, Open LTR - 1^st phase, A High Speed Logarithmic Arithmetic Unit, May 1997. This is a grant proposal that outlines research conducted at the University of Newcastle upon Tyne. For more information, refer to www.cordis.lu/esprit/src/23544.htm. [ bib ]
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